Optional Relay-Controlled Preamp: Precision You Can Add or Remove

The Spring 3 offers a fully discrete, balanced, relay-controlled volume control, providing precise management of all digital input levels. This design incorporates trickle-down technology from Holo Audio’s flagship Serene preamp, utilizing four amplifier modules and hundreds of carefully matched transistors for exceptional performance.

The preamp stage is optional and can be added or removed later, but this service is only available at Magna Hifi. Installing or removing the preamp requires special tools and circuit modifications, so it cannot be performed elsewhere, ensuring the DAC maintains its integrity and highest level of performance.

Native DSD and High-Resolution PCM Playback

The Spring 3 DAC (all three models) supports native DSD1024 and PCM up to 1.536 MHz. In theory, it is capable of reaching DSD2048 and PCM 3.072 MHz, though these extreme modes remain untested. A specially designed circuit has also been implemented to greatly reduce the common clicking noise that often occurs in DACs when switching between DSD and PCM formats.

Holo Audio was the world’s first to achieve true native DSD playback on an R2R DAC—and remains the only one to do so. Unlike other solutions that convert DSD to PCM before analog conversion, the Spring 3 processes DSD directly through discrete components for uncompromised purity. Native DSD is currently supported on macOS (DoP), Linux (DoP), and Windows/PC (Direct Native and DoP).

There are ways to improve the performance, the segment+R2R is one way. Trimming is another way. There is an additional R2R ladder in Spring, it compensate the main R2R ladder. It works like trimming, but trimming is to change the resistor value. This additional R2R ladder are digital controlled and is to compensate the resistor tolerance. For example, the MSB of 16 bits should have the value of 32768, but due to tolerance, it represent 32700 in real world. Then that additional R2R ladder will compensate 68 into it. Then it became 32700+68=32768.

Design executed to perfection

Actually there are other ways to improve performance, I just told you two stories. There are more stories behind the design. It is really hard. I must count every via holes in layout, every PCB wire has it’s impedance and must put attention on it. A via hole can be 50 m Ohm, it is 1/20000 of 1 kilo-ohm, and you see, it covers 32768 which is the MSB of 16bits. Also the switches has self-impedance which is about several ohms to 30 ohms. If you find this issue. Maybe you will go crazy, it seems to be an impossible mission. But a good designer will overcome all these problems. It’s our value at HOLO Audio.

All the resistor tolerance, switch impedance, line impedance, via hole impedance, finally reflect as linearity. There is a chart that shows Spring’s linearity, it’s excellent. But I suggest you to look at THD performance. Bad linearity must result a bad THD performance. But good linearity doesn’t mean there will be good THD performance. THD is dynamic performance, more critical than linearity which is a static performance.

If you look at the THD performance, you will find Spring to maybe the best among those competitors. I’m applying a patent which contribute a lot of that performance. But I can’t tell you how. It’s confidential now.

Custom PLL for Ultra-Low Jitter Performance  

The Holo Audio Spring 3 DAC is equipped with a fully custom, high-performance PLL (phase-locked loop) circuit engineered for ultra-low jitter. Even extreme levels of jitter are effectively suppressed, ensuring exceptional sound quality and musical clarity. At the core of this system are precision Crystek VCXO clocks, which reclock incoming digital signals with remarkable accuracy. This advanced PLL can be engaged or bypassed, allowing listeners to hear its impact firsthand, and unlike standard off-the-shelf solutions, it represents one of the most powerful PLL implementations in any DAC to date.

Why SPDIF and Toslink Introduce Jitter

SPDIF, a protocol developed in the 1970s for CDs by Sony and Philips, encodes data and clock signals together, allowing transmission over a single cable. While convenient, this encoding process introduces jitter, and Toslink, the fiber-optic version of SPDIF, adds further timing errors during electronic-to-optical and optical-to-electronic conversion. By contrast, I2S separates the signals—three clocks and one data line—avoiding encoding-related jitter entirely, making it a superior interface for high-performance playback.

To mitigate jitter from SPDIF, a PLL uses a local clock to track the source signal and smooth timing deviations. For example, if the source alternates between 44,101 Hz and 43,999 Hz, a weak PLL might only partially correct it, while May’s high-performance PLL locks the clock to within micro-Hz of the ideal 44,100 Hz. Standard SPDIF chips, like the AK4118A, achieve around 50 ps jitter, which is excellent for commercial chips but far from the HiFi standard May aims for. Achieving stronger PLL performance is extremely challenging, requiring a precise local clock that can adjust to the source in real-time.

FIFO Buffering: Preserving Every Sample

Instead of using a common VCO, May employs a VCXO (Voltage-Controlled Crystal Oscillator)—specifically Crystek’s CVHD-957—providing unmatched stability and precision. Synchronizing the data with this clock is equally critical: incoming samples fluctuate due to source jitter, and a simple digital filter like an ASRC would modify the data, compromising bit-perfect accuracy. May solves this with a sophisticated FIFO buffer system, storing extra samples during high-frequency jitter periods and releasing them during low periods, preserving every bit of data perfectly.

Unmatched Long-Term Stability and Jitter Reduction

The result is a PLL with a corner frequency of 0.05–0.1 Hz across three orders, capable of reducing long-term jitter by 90%, 1-second jitter by 99%, and 0.1-second jitter by 99.9%. Unlike many industrial PLLs that unlock under extreme jitter, May’s system maintains a stable lock, ensuring uninterrupted, distortion-free playback even in the most challenging conditions. This combination of precision clocking and intelligent data handling makes May’s PLL one of the most powerful and effective ever designed for a DAC.

Non Oversampling (NOS) for Ultimate Sound

NOS mode, without oversampling, the original data directly to the analog conversion. NOS can avoid these problems because digital oversampling can produce time-domain distortions such as ringing effects. NOS will usually have a significant impact on other performance indicators, but the spring design can make the NOS mode also maintain a good performance indicators.

Digital input interface, including, USB (ground isolation), RCA, BNC, AES, optical fiber, HDMI interface, I2S. All digital input interfaces support DSD (DOP mode). Spring analog output interface for the single-ended and balanced each group.